Design For Testability

BALU Technology offers DFT design, Scan Insertion & Stitching, Boundary Scan, MBIST, LBIST, IP Creation & Integration, Formal Verification before and after DFT.

BALU Technology Services During Design Phase

Our DFT team collaborates with design team in parallel. We offer:

Design DFT Architecture

Scan Insertion

Fault injection and pattern generation

Coverage Analysis and Pattern Simulation with the Scan Inserted Netlist

BALU Technology Services After Design Phase

Our DFT team collaborates with design team in parallel. We offer:

Test Patterns Generations to Detect Faults

Layout-Aware Diagnosis

Ensure the Quality of Mass Production

OUR COMPETENCY

- Design DFT Architecture
- Scan Implementation (Compression/Non-Compression) Using Industry Standard Tools
- Boundary Scan, MBIST, LBIST
- Test Point Insertion, X bounding
- Compression logic IP creation and synthesis (EDT, EDT Bypass)
- Formal Verification before and after DFT
- JTAG IEEE 1149.1, IEEE1149.6 Standard compliance test controllers
- ATPG (Stuck-at, At-speed, SDD, Path Delay, New faults)
- Creation of Vectors Pattern (Verilog, WGL)
- Low Power ATPG
- Post Silicon Diagnosis: Scan diagnosis, Layout Aware Diagnosis (LAD)
- PLL clocks on the Chip were utilized for testing
- Coverage Analysis and Pattern Simulation with the Scan Inserted Netlist